library verilog;
use verilog.vl_types.all;
entity doors is
    port(
        A               : in     vl_logic;
        B               : in     vl_logic;
        NotGate         : out    vl_logic;
        AndGate         : out    vl_logic;
        OrGate          : out    vl_logic;
        NandGate        : out    vl_logic;
        NorGate         : out    vl_logic;
        XorGate         : out    vl_logic;
        LedNotGate      : out    vl_logic;
        LedAndGate      : out    vl_logic;
        LedOrGate       : out    vl_logic;
        LedNandGate     : out    vl_logic;
        LedNorGate      : out    vl_logic;
        LedXorGate      : out    vl_logic
    );
end doors;
